C and Perl

 

How do you Print the system time in C and Perl to an output file ??

How do you open files in C , Perl, Verilog and VHDL ??

 

 

DRP -> Platform -> SDR

Todays DRP lecture was very nice. It was the first time I directed my attention towards the buzzy concept of a platform. I have heard this word being mentioned in the context of FPGAs. Maybe I began to wonder too, what it was about but then never invested too much thought into it.

Khurram introduce the concept very nicely today. DRP is a design philosophy. The forst impression I carried of DRP was that it was nothing but doing processing in the digital domain and moving away from all that is analog as much as possible. Though this is a good enough first impression I think the chief features of DRP lurk behind the facade of digital vs analog or the single chip radio. The name , though not a misnomer is misleading too.

The thought behind the DRP philosophy is to harness the synergy between the various components of a Radio and use this synergy to solve the generic problem of implementing a radio. Synergy is again misleading, a more accurate word would be unification across modular boundaries. What I am trying to get at is that, under the aegis of DRP we would have hard ( not programmable) components being able to talk to the softest components (DSP/uP highly programmable) across the system. This would throw up possibilties of more efficient solutions for the problem. Ability to make the components softer helps solve the problem for a number of radio designs. So a platform is nothing but an architecture which would enable
a) Efficient communication across module boundaries of a radio.
b) Exploiting the soft nature of components to help other modules be more efficient and softer.

Developing such a platform would mean that we need to understand what kind of softness to build into these hard components. This can be arrived at only after studying a lot of radio designs. Once we have the knowledge of what soft features we want these components to have we can then design the communication infrastructure between these components.

Once the platform is defined we can have a SOFTware defined radio within the limitations of the platform.

The concept of platform also throws up something which I can do with leakage. What I am building is a platform to build applications such that we can map high speed and low power circuits at the same time.

Gray to Binary Code

Here is one algorithm to convert from "natural binary codes" to Gray
code (encode):

Let B[n:0] the array of bits in the usual binary representation
Let G[n:0] the array of bits in gray code
G[n]=B[n]
for i=n-1 down to i=0 {
G[i]=B[i+1] XOR B[i]
}

Here is one algorithm to convert from Gray code to "natural binary codes" (decode):

    B[n]=G[n]

  for i=n-1 down to i=0 {

    B[i]=B[i+1] XOR G[i]

  }

Finding power in TI-SPICE

Example 6
P(Q1 Q2,TA X1.M1,TA)
P(Q1) P(Q2,TA) P(X1.M1,TA)
P(X1.X2)
The two lists above are equivalent. The following variables are selected:
❏ The instantaneous power dissipated by BJT Q1
❏ The time average power dissipated by BJT Q2 (for transient analysis)
❏ The time average power dissipated by MOSFET M1 in subcircuit X1
(for transient analysis)
❏ Tht sum (algebraic) of the instantaneous power in all devices in
subcircuit "X1.X2"

PT or XG based MUX

When designing a 4:1 Mux which is better a Pass Transistor based or a
Transmission Gate ?

Area : PT is better
Delay : XG might be better and more symmetric
Power : PT would be better because of less cap and less VDD transition levels.


--

2/n-variable theorems

Covering theorem : a+aX = a , since a already covers the following minterm
Distributivity: x=yz = (x+y)(x+z)
Consensus Theorem : ab+a'c+bc = ab+a'c

Priniciple of Duality : Any theorem or identity remains true if 0 and
1 are swapped and . and + are swapped throughout.

Static Hazards

ab+a'c+bc
This can actually be reduced to ab + a'c which is nothing but a Mux.
This is a good example of how a circuit can glitch.
In this mux if b=c=1 and a switches from 1 to 0 then the output should
remain at 1. However due to the inverter delay between a and a' the
expression will be '0' for a duration = delay of the inverter. This
will give a glitch at the output. By including the the term ab in the
implementation this hazard can be avoided.

What is meant by associativity of a cache ??

What is meant by associativity of cache ??
How does it affect the performance of cache ??

Dynamic PD at nodes driven by sources.

For the CMOS circuit given below, estimate the total power dissipation.
Four inputs of this circuit, ABCD are stimulated repeatedly by the following
sequence of input vectors (one vector every 10ns):
1110, 1111, 1101, 1111, and 1100. Assume a supply of 3.3V,
an average leakage current of 10nA per gate; that each MOSFET has a
gate capacitance of 50fF, and this circuit drives an output load of 1pF.
What is the logic function implemented by this circuit?



For this circuit should we consider the CV2f power at the A,B,C and D nodes.

No becuase they are driven by the source and there is no power dissipation in any of the semiconductor devices. All the power from the source is transferred to the caps at these nodes and back from these nodes to the source.

SOP to POS

Any SOP to POS conversion can be done by repeatedly using a+bc= (a+b)(a+c)