Links to question sites

http://www.hitequest.com/Hardware/El_hardware.htm

http://www.deeps.org/verilog/questions.html

http://www.asic-world.com/digital/questions.html

http://www.aviral.co.uk/q.html

http://www.parmita.com/verilogcenter/quest.html

Why global signals use upper layers ??

If you see the wafer, top metal has more no. of up & downs this means
we need to make then wider.
Because of its wider shape it will give less resistance as compared to
bottom metal i.e it will give less IR drops there for it is used for
global routing, like power, as u said.

Comparator , |A-B|

Which is a better implementation of
1. A comparator
a) Subtractor along with sign examination logic.
b) Comparator from its truth table.
How does XST and DC implement a description of a comparator in Verilog.

2. mod (A-B)
do we just describe this as
[ comparator -> select line of mux
b-a and a-b as two inputs of a mux ]

if(a <= b)
out <= b-a;
else
out <= a-b;


----------------------

Multiplier using a ROM ??

When (for how large an operand size) does the area of a multiplier
implemented by ROM become larger than the area of a multiplier
implemented by adders ??

Or is there a clear advantage of having adder based multipliers ??

Question :
--------------
To realise a 2 input(each input is 4 bit) multiplier using a ROM and
what will be the size of the ROM. How can you realise it when the
outputs are specified.

Hint
Use the ROM as LUT (look up table );
Inputs will be assigned as ROM address lines of 8 bits .
each memory word will be 8 bits as the maximum output of the
multplication is 15X15 = 225 (fits in 8 bits )
for instance if we multpliy 15 X 2 the address line will be 1111-0010
the word corresponding to this address in memory should store a value
of 30 decimal in binary 0001-1110 What is tricky here is that the
multiplication is cummutative , i.e , 15 X 2 = 2 X 15
what if the address has now 0010-1111 it should point to a word in the
lower half of the ROM table and what is tricky is that it should hold
the same binary value of 30 decimal =0001-1110 .
The ROM size in my point of view is 2 ^^ 8 = 256 words though we store
only 128 word but we have to duplicate every word ; one time at the
lower half and the other time at the upper part.

Although it seems to make sense , the above observation is wrong we
need to store (256-16)/2 +16 = 120 + 16 = 136 values.

We can still implement this using a 128 entry ROM , using a complex
mapping mechanism of the addresses if we can somehow take care of all
the trivial cases of multiplication by 1 and 2.

-Rajan

Inverter Transfer Characteristics

Q. How do you define the Noise Margin of an inverter ??
Noise Margin from the Transfer Characteristics
NMH = VOH-VIH = VDD - VM
NML = VIH-VOH = VM - GND

This is because when the input crosses VM the output switches to the other state. This indicates that we cannot tolerate any noise more than VM on the input lines.

To have NMH=NML we should have VM= VDD/2.

Q. How do we set the slope of the inverter TC ??
The slope is nothing but the gain in the saturation region and thus it depends on the 'gm' of the
NMOS and the 'ro' of the PMOS.
gm = sqrt(2.Id.K'.W/L) , so increasing the W/L of the NMOS will increase the slope.
ro = K/lambda.Id , so reducing Id will increase the total gain, we can do this by reducing VDD.

Q. Why would someone want to increase the slope of the transition region ??
The current for both NMOS and PMOS is maximum in the saturation region.
Both the NMOS and the PMOS are turned on in the transition region. This means that a lot of static power is being burnt if the transistors spend more time in this region.

Of course the savings in static power will be traded off with area and maybe speed too.

Digital vs Analog

Why do we not care about changing the lengths of the transistors in Digital circuit design ??