Write-invalidate vs Write-update CC protocols

Automatic Verification of Parameterized Cache Coherence Protocols: "In a shared-memory multiprocessor system local caches are used to reduce memory access latency and network traffic. Each processor is connected to a fast memory `backed up' by a large (and slower) main memory. This configuration enables processors to work on local copies of main memory blocks, greatly reducing the number of memory accesses that the processor must perform during program execution. Although local caches improve system performance, they introduce the cache coherence problem: multiple cached copies of the same block of memory must be consistent at any time during a run of the system.

A cache coherence protocol ensure the data consistency of the system: the value returned by a read must be always the last value written to that location (cf. [AB86,Han93]). Coherence policies are typically described as finite state machines that specify the way a single cache reacts to events like read and write requests. As an example, let us consider a CC-UMA (Uniform-Memory-Access with local Caches model) multiprocessor system, i.e., a system in which all processors have a local cache connected to the main memory via a shared bus. In write-invalidate protocols whenever a processor modifies its cache block a bus invalidation signal is sent to all other caches in order to invalidate their content. In write-update protocols, instead, a copy of the new data is sent to all caches that share the old data."