Reasons for System Verilog logic and reg types

Verification Guild: "logic is identical to reg
I'm trying to determine what the intent was regarding the definition of logic-type variables compared to reg-type variables in System Verilog. I have not found anything definite in the more recent LRMs that indicate any difference at all -- they are both simply 4-state variables. Are there any cases laid out by the LRM where a logic variable is allowed but a reg-type is not (and vise versa)? We have come up with some of our own ideas regarding how they could be used to help imply design intent (combinational vs. synchronous variables, for example) but nothing that would be enforced by a compiler/parser.

I believe "logic" was added to remove the reg/wire duality. i..e. a variable declared as type logic can be assigned to procedurally OR with a continous assignment (not both). So logic is now your universal four state type. No more rules on whether a variable needs to be declared as wire, or reg - just use logic.

The logic type is UNRESOLVED - meaning there's no support for multiple drivers. 99% of the time this is a don't care since on todays SOCs in sub 0.25 um technology, there aren't any internal tri-states anyway. You'll really only need to use those wires along the periphery of the chip where there are true multi-driver nets.

A lot of new users assume reg will infer a hardware register. In fact, reg is a generic storage type that can be a register or combinational logic. So the logic type name was kept to eliminate the ambiguity. While the names are completely interchangeable, I expect the experts will encourage us all to use logic instead or reg from now on."

[Furled]