Intel sells XScale business to Marvell for $600m | Reg Hardware

Intel sells XScale business to Marvell for $600m | Reg Hardware: "Intel is to flog off its XScale processor operation, the chip giant said today. The move paves the way for it to push low-power x86 CPUs at mobile phone and PDA makers. The buyer is comms chip company Marvell Technology Group, which is paying $600m cash for the product line and taking on 'certain liabilities'.

The deal covers the full XScale line-up, including the PXA9xx series of mobile phone chips and the PXA27x line aimed at PDAs. Intel has some 1,400 staff working on and around the XScale family, many of whom it expects will leave Intel and join Marvell, Intel said - handy for the chip giant's restructure plans. Selling the business had been forecast by analysts."

Apple to boost iTunes downloads with BitTorrent? | Reg Hardware

Apple to boost iTunes downloads with BitTorrent? | Reg Hardware: "Apple's next major operating system release - aka 'Leopard' - will feature built-in BitTorrent support to speed up the company's eagerly anticipated movie download service, it has been alleged. If true, it would allow iTunes Music Store customers to grab video data not only from the online shop but also from other customers who've already purchased the movie.

Readers assuming this marks Apple's whole-hearted embrace of P2P technology should remember that downloaded movies will still be DRM'd to the hilt. The move is more about getting content to customers more quickly than sharing stuff."

IBM overclocks chip to 500GHz | Reg Hardware

IBM overclocks chip to 500GHz | Reg Hardware: "Boffins from IBM and the Georgia Institute of Technology (GIT) have produced what they claim is the world's fastest silicon chip thanks to what must be the acme of overclocking. The researchers reached a clock speed of 500GHz by reducing its temperature to just 4.5° above absolute zero.

The feat was part of the team's exploration of fourth-generation Silicon-Germanium (SiGe) devices, which IBM and GIT are investigation for future comms chip applications. The scientists wanted to see just how fast such a chip could be persuaded to run without malfunctioning or, in extreme cases, melting."

EETimes.com - IEEE catches the Spirit of IP reuse

EETimes.com - IEEE catches the Spirit of IP reuse: "There's more to Spirit than what first meets the eye, said Gary Smith, chief EDA analyst at Gartner Dataquest. 'Spirit has grown from a fairly boring standards effort to an extremely exciting effort over the past few years,' he said.

Beyond IP metadata, Smith said, the technical community is looking at Spirit as a way to embed constraints from the behavioral level down to RTL implementation. Some, he said, are looking at Spirit as a way of developing the 'intention layer' needed to imply parallelization for C-language code. That means Spirit could be an important part of what Smith calls the 'concurrent software compiler,' a future development that will be important for large-scale multiprocessor SoC design."

MESI protocol - Wikipedia, [tech concepts]

MESI protocol - Wikipedia, the free encyclopedia: "The MESI protocol (known also as Illinois protocol) is a widely used cache coherency and memory coherence protocol, which was later introduced by Intel in the Pentium processor to 'support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor'.
Every cache line is marked with one of the four following states (coded in two additional bits):

* M - Modified: The cache line is present only in the current cache, and is dirty; it has been modified from the value in main memory. The cache is required to write the data back to main memory at some time in the future, before permitting any other read of the (not longer valid) main memory state.
* E - Exclusive: The cache line is present only in the current cache, but is clean; it matches main memory.
* S - Shared: Indicates that this cache line may be stored in other caches of the machine.
* I - Invalid: Indicates that this cache line is invalid.

A cache may satisfy a read from any state except Invalid. An Invalid line must be fetched (to the Shared or Exclusive states) to satisfy a read.
A write may only be performed if the cache line is in the Modified or Exclusive state. If it is in the Shared state, all other cached copies must be invalidated first. This is typically done by a broadcast operation.
A cache may discard a non-Modified line at any time, changing to the Invalid state. A Modified line must be written back first.
A cache that holds a line in the Modified state must snoop (intercept) all attempted reads (from all of the other CPUs in the system) of the corresponding main memory location and insert the data that it holds. This is typically done by forcing the read to back off (i.e. to abort the memory bus transaction), then writing the data to main memory and changing the cache line to the Shared state.
A cache that holds a line in the Shared state must also snoop all "

Freescale Power Architecture

Freescale Power Architecture: "The word is out: Freescale and IBM are collaborating on the continuing evolution of Power Architecture™ technology – the most comprehensive microprocessor architecture on the market. IBM and Freescale share a long heritage in the evolution of Power Architecture technology, including the PowerPC® instruction set, and a common vision for its future.

In devoting resources, both companies indicate a strong future for Power Architecture technology. As part of that support, Freescale has joined Power.org as a founding member and joins IBM in forming the Power Architecture Advisory Council (PAAC). Managed evolution of the Power Architecture ISA will take place within the PAAC – enabling broad community input, greater consistency, and keen focus on the future direction of Power Architecture.

As a licensee and developer of PowerPC™ cores and products since 1993, Freescale has been active in the proliferation of Power Architecture in a broad spectrum of markets: automotive, consumer, networking, storage and industrial.

Did you know that Power Architecture technology is at the heart of engine control, enabling a wide range of automotive applications including body, advanced safety and driver information systems By 2007, approximately 50 percent of car models in the world will contain Power Architecture-based chips. And Freescale will be there with its Automotive Microcontrollers based on Power Architecture."

www.linux-nis.org (NIS Server and Tools)

www.linux-nis.org (NIS Server and Tools): "The Network Information Service (NIS) provides a simple network lookup service consisting of databases and processes.

At first you need to define the NIS master server which contains all source files for the various maps like /etc/passwd, /etc/group or /etc/hosts. The NIS server process ypserv needs to be run on this host. The ypserv daemon is typically activated at system startup. There could be more hosts running ypserv, this one are called 'slaves'. They get their maps from the master server. If a slave goes down, it will miss updates from the master.

On other machines using the NIS services as client, you have to run ypbind. ypbind must run on every machine which has NIS client processes; ypserv may or may not be running on the same node, but must be running somewhere on the network. For normal users, you need the yp-tools. This package provide tools for communication with ypbind, ypset and ypwhich, tools for accessing the NIS maps, ypcat, ypmatch and yppoll, and tools for changing NIS user information, ypchfn, ypchsh and yppasswd.

The ypserv package implements fully NIS master/slave support and is compatible to the version from SUN. The YP V2 protocol is complete implemented, YP V1 only partially. ypbind-mt implements a multi-threaded ypbind daemon, which is compatible to the SUN ypbind protocol version 1 and 2. Version 3 is not supported, since the protocol is not publically available. The yp-tools supports only the YP and ypbind protocol version 2."

Google Search: define: daemon

Google Search: define: daemon: "Definitions of daemon on the Web:

* A daemon is a program that runs, without human intervention, to accomplish a given task. For example, lpd is a daemon that controls the flow of print jobs to a printer.
www.redhat.com/docs/manuals/linux/RHL-6.2-Manual/getting-started-guide/ch-glossary.html

* A program that runs in the background; that is, without user interaction.
www.oreilly.com/catalog/debian/chapter/book/glossary.html

* A program that runs unattended to perform continuous or periodic systemwide functions, such as network control.
www.sabc.co.za/manual/ibm/9agloss.htm"

Write-invalidate vs Write-update CC protocols

Automatic Verification of Parameterized Cache Coherence Protocols: "In a shared-memory multiprocessor system local caches are used to reduce memory access latency and network traffic. Each processor is connected to a fast memory `backed up' by a large (and slower) main memory. This configuration enables processors to work on local copies of main memory blocks, greatly reducing the number of memory accesses that the processor must perform during program execution. Although local caches improve system performance, they introduce the cache coherence problem: multiple cached copies of the same block of memory must be consistent at any time during a run of the system.

A cache coherence protocol ensure the data consistency of the system: the value returned by a read must be always the last value written to that location (cf. [AB86,Han93]). Coherence policies are typically described as finite state machines that specify the way a single cache reacts to events like read and write requests. As an example, let us consider a CC-UMA (Uniform-Memory-Access with local Caches model) multiprocessor system, i.e., a system in which all processors have a local cache connected to the main memory via a shared bus. In write-invalidate protocols whenever a processor modifies its cache block a bus invalidation signal is sent to all other caches in order to invalidate their content. In write-update protocols, instead, a copy of the new data is sent to all caches that share the old data."

Symmetrical Multi-Processing

Symmetrical Multi-Processing: "One of the easiest and cheapest ways to improve hardware performance is to put more than one CPU on the board. This can be done either making the different CPU's take on different jobs (asymmetrical multi-processing) or by making them all run in parallel, doing the same job (symmetrical multi-processing, a.k.a. SMP). Doing asymmetrical multi-processing effectively requires specialized knowledge about the tasks the computer should do, which is unavailable in a general purpose operating system such as Linux. On the other hand, symmetrical multi-processing is relatively easy to implement.

By relatively easy, I mean exactly that: not that it's really easy. In a symmetrical multi-processing environment, the CPU's share the same memory, and as a result code running in one CPU can affect the memory used by another. You can no longer be certain that a variable you've set to a certain value in the previous line still has that value; the other CPU might have played with it while you weren't looking. Obviously, it's impossible to program like this.

"