MESI protocol - Wikipedia, [tech concepts]

MESI protocol - Wikipedia, the free encyclopedia: "The MESI protocol (known also as Illinois protocol) is a widely used cache coherency and memory coherence protocol, which was later introduced by Intel in the Pentium processor to 'support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor'.
Every cache line is marked with one of the four following states (coded in two additional bits):

* M - Modified: The cache line is present only in the current cache, and is dirty; it has been modified from the value in main memory. The cache is required to write the data back to main memory at some time in the future, before permitting any other read of the (not longer valid) main memory state.
* E - Exclusive: The cache line is present only in the current cache, but is clean; it matches main memory.
* S - Shared: Indicates that this cache line may be stored in other caches of the machine.
* I - Invalid: Indicates that this cache line is invalid.

A cache may satisfy a read from any state except Invalid. An Invalid line must be fetched (to the Shared or Exclusive states) to satisfy a read.
A write may only be performed if the cache line is in the Modified or Exclusive state. If it is in the Shared state, all other cached copies must be invalidated first. This is typically done by a broadcast operation.
A cache may discard a non-Modified line at any time, changing to the Invalid state. A Modified line must be written back first.
A cache that holds a line in the Modified state must snoop (intercept) all attempted reads (from all of the other CPUs in the system) of the corresponding main memory location and insert the data that it holds. This is typically done by forcing the read to back off (i.e. to abort the memory bus transaction), then writing the data to main memory and changing the cache line to the Shared state.
A cache that holds a line in the Shared state must also snoop all "

Freescale Power Architecture

Freescale Power Architecture: "The word is out: Freescale and IBM are collaborating on the continuing evolution of Power Architecture™ technology – the most comprehensive microprocessor architecture on the market. IBM and Freescale share a long heritage in the evolution of Power Architecture technology, including the PowerPC® instruction set, and a common vision for its future.

In devoting resources, both companies indicate a strong future for Power Architecture technology. As part of that support, Freescale has joined Power.org as a founding member and joins IBM in forming the Power Architecture Advisory Council (PAAC). Managed evolution of the Power Architecture ISA will take place within the PAAC – enabling broad community input, greater consistency, and keen focus on the future direction of Power Architecture.

As a licensee and developer of PowerPC™ cores and products since 1993, Freescale has been active in the proliferation of Power Architecture in a broad spectrum of markets: automotive, consumer, networking, storage and industrial.

Did you know that Power Architecture technology is at the heart of engine control, enabling a wide range of automotive applications including body, advanced safety and driver information systems By 2007, approximately 50 percent of car models in the world will contain Power Architecture-based chips. And Freescale will be there with its Automotive Microcontrollers based on Power Architecture."