Predecoding

The idea is to speed up the decoding process by using gates with less
fan in. To reduce delay we will use two levels of decoding. This is
also likely to reduce the routing complexity. The first level of
decoding called pre-decoding. However I am unable to explain why we
cannot use Pass transistor based decoders with buffers inserted at
appropriate levels. For an FPGA pre-decoding for a 4-LUT is not a very
attractive idea since we will have more leakage with negative or no
impact on the delay in the read path.

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Segue : Why does speed of the gate decrese with increse in fan-in ??
This degradation will be exponential too , since in either the pull-up
or pull-down we will be increasing the series resistance. To keep the
delay in control we will size the transistors larger and this might
load the previous stage of logic.

Ref : Xilinx LUT architecture , US Patent 6,445,209 B1

Probability of output state of a circuit

Given any circuit we might need to find the probability of the output
being high or low. This is a very common problem in determining the
dynamic power , in order to predict the probability of switching at
the output of any gate. I was under the impression that this can be
done by using the characterictic equation of the circuit.

For example , an AND gate has Y= A.B. Lets say the probability of '1'
for each of the inputs is 0.5. This means that the probability of '0'
for these inputs is also 0.5.Now if we want to calculate the
'probability of the output of this AND gate being '0' , we cannot
claim it to be 'P(A=0) x P(B=0).
However it can be P(A=0) + P(B=0/A=1) = 0.5 + 0.25 = 0.75.

I was thinking of a scalable/repeatable model ,i.e since any function
can be written in terms of SOP :
(i) Calculate probability of the output of n-input AND gates if we
know the dependence of the input signals.
(ii) Calculate probability of the output of n-input OR gates if we
know the dependence of the input signals.