Predecoding

The idea is to speed up the decoding process by using gates with less
fan in. To reduce delay we will use two levels of decoding. This is
also likely to reduce the routing complexity. The first level of
decoding called pre-decoding. However I am unable to explain why we
cannot use Pass transistor based decoders with buffers inserted at
appropriate levels. For an FPGA pre-decoding for a 4-LUT is not a very
attractive idea since we will have more leakage with negative or no
impact on the delay in the read path.

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Segue : Why does speed of the gate decrese with increse in fan-in ??
This degradation will be exponential too , since in either the pull-up
or pull-down we will be increasing the series resistance. To keep the
delay in control we will size the transistors larger and this might
load the previous stage of logic.

Ref : Xilinx LUT architecture , US Patent 6,445,209 B1