IC Design <= (Logic Design | Semiconductors | Evolving Technology | Architecture | EDA ) ;

Wednesday, September 08, 2004

Static Hazards

ab+a'c+bc
This can actually be reduced to ab + a'c which is nothing but a Mux.
This is a good example of how a circuit can glitch.
In this mux if b=c=1 and a switches from 1 to 0 then the output should
remain at 1. However due to the inverter delay between a and a' the
expression will be '0' for a duration = delay of the inverter. This
will give a glitch at the output. By including the the term ab in the
implementation this hazard can be avoided.

0 Comments:

Post a Comment

<< Home