Death of Logic Synthesis

"To logic synthesis people, the message is clear," said Madhavan. "Resistance is futile. You will be assimilated."
Excerpt :
" To reduce the cost of silicon as feature sizes shrink, Madhavan said, EDA vendors will need to provide automated RTL-to-GDSII design systems, not collections of individual tools. And for new process geometries, he said, most optimization decisions will need to be made during routing, well downstream from today's logic synthesis. "

This is an interesting direction that logic synthesis is taking. Ofcourse it looks like this would give us better results. It would also remove all the post-synthesis verification and timing closure loops. What are the downfalls if any of this development ??