System Verilog - static vs automatic variables

A variable can be static (storage allocated on instantiation and never de-allocated) or automatic (stack storage
allocated on entry to a scope (such as a task, function or block) and de-allocated on exit). C has the keywords
static and auto. SystemVerilog follows Verilog in respect of the static default storage class, with automatic
tasks and functions, but allows static to override a default of automatic for a particular variable in such
tasks and functions.